Here the last few decades, Network on Chip’s are the powerful chips for high speed\r\ncommunications pertaining to 802.11 Ethernet protocol which is , need to be reconfigurable for\r\nsuccessful data frame transmission. The existing architectures like coarse grained reconfigurable,\r\nALU cluster and expression grain reconfigurable architecture and look-up-table used in fine\r\ngrained reconfigurable devices require a lot of storage memory, hardware possessions such as\r\nslices, cell area and cell delay. To tackle these issues, Multi grained Reconfiguration and Parallel\r\nMapping Architecture is proposed and their performance analysis parameters are premeditated.\r\nThe MRPMA uses the four contributions to optimize Processing Elements operations: 1) Fast\r\nFourier Transformation to perform fixed point numbers to the configuration words, 2) Discrete\r\nCosine Transformation to analyze the data in the frequency domain, 3) Finite Impulse Response\r\nfor parallel mapping the data and 4) Channel encoder and decoder to encode the data and to\r\ncalculate the shortest route from source to destination switch.

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