Tremendous revolutionary changes lead the electronic industry from the past eight decades. Nowadays, portable electronic systems play a major role in the human life. These systems consist of adders, multiplexers, registers, memories etc. But memories are more power consuming components in embedded applications. In general, embedded systems are equipped with large battery sources in order to avoid frequent charging of batteries. The capacity of the battery depends on the power consumption of the system. Higher the power consumption can higher the battery capacity and hence the size which is unacceptable for portable embedded systems. So we need effective low power VLSI techniques for better performance of integrated systems. Many authors propose low power techniques for design and implementation of systems; the most effective energy saving method is low voltage operation. Heterojunction tunneling structures operated in the low subthreshold region of the transistor. This work presents the analysis of different types of heterojunction tunneling architectures for low power as well as ultra low power applications. A comparative analysis of heterojunction architectures can be done with reference to ION / IOFF ratio, leakage current, subthreshold swing (SS) and materials used for manufacturing and it needs a trade-off among these parameters. So, we proposed an architecture that addresses High ION / IOFF ratio, steeper subthreshold swing and improved Miller capacitance with less leakage current. These structures give a great compromise between power consumption and performance (speed and power trade-off) and hence improving the performance of heterojunction architectures.

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